With the rapid advancement of data centres, artificial intelligence, and high-performance computing, PCIe (PCI Express) has emerged as the dominant high-speed serial bus standard. Its data transfer rates have evolved from 8GT/s in PCIe 3.0 to 32GT/s in PCIe 5.0, and even 64GT/s in PCIe 6.0. At such elevated data transmission speeds, signal integrity issues become critical factors affecting system stability and performance.

This paper will delve into the importance of PCIe signal integrity testing, its scope, and implementation methods, helping engineers better understand and address the challenges of high-speed digital signal testing.

Why is PCIe signal integrity testing so crucial?

Challenges posed by high data rates

Increased PCIe signal transmission rates entail shorter rise times and higher frequency components. This exacerbates the following issues:

Crosstalk effects: heightened electromagnetic interference between adjacent signal lines

Reflection loss: signal reflections caused by impedance discontinuities

Insertion loss: Attenuation of high-frequency signals along the transmission path

Jitter accumulation: Timing deviations in clock and data signals

Inter-symbol interference (ISI): Mutual interference between symbols at high data rates

The Value of Testing

Systematic signal integrity testing enables:

Early detection of design flaws, reducing costly later modifications

Ensuring product compliance with PCIe specification requirements

Enhanced system reliability and interoperability

Optimisation of signal transmission path design

I. Core Elements of PCIe Signal Integrity Testing

1. Eye Diagram Testing

The eye diagram provides the most intuitive method for evaluating signal quality. It displays multiple data cycles of the signal waveform superimposed to form an eye-shaped pattern.

Key Parameters:

Eye Height: Reflects signal amplitude margin

Eye Width: Reflects timing margin

Eye Opening: Provides a comprehensive assessment of signal quality

Test Methodology:

Employ a high-bandwidth oscilloscope with clock recovery capability to capture differential signals at the transmitter or receiver end. Superimpose these signals to generate the eye diagram. A robust eye diagram exhibits a distinct aperture and conforms to the mask specified by PCIe standards.

2. Jitter Analysis

Jitter denotes the temporal deviation of signal edges from their ideal position, constituting a critical factor in high-speed signal transmission.

Jitter Classification:

Random Jitter (RJ): Caused by random factors such as thermal noise, exhibiting a Gaussian distribution

Deterministic Jitter (DJ): Caused by deterministic factors such as crosstalk and reflections

Total Jitter (TJ): The combination of RJ and DJ

Test Metrics:

Tx Output Total Jitter (TJ)

Tx De-Embedded Jitter

Rx Tolerated Jitter

3. S-parameter Testing

S-parameters (scattering parameters) describe the frequency-domain characteristics of signals within transmission paths and serve as critical metrics for evaluating channel quality.

Key Parameters:

Insertion Loss (IL): S21, representing signal attenuation through the channel

Return Loss (RL): S11, indicating the degree of signal reflection

Crosstalk: NEXT (Near-End Crosstalk) and FEXT (Far-End Crosstalk)

Test Methodology:

Measure PCIe channel S-parameters using a vector network analyser (VNA) to evaluate the complete transmission path from transmitter to receiver, encompassing connectors, PCB traces, vias, etc.

4. Equalisation Testing

To compensate for high-frequency signal attenuation, PCIe employs equalisation techniques:

Transmitter De-emphasis: Used in PCIe 3.0/4.0

Continuous-Time Linear Equaliser (CTLE): Receiver equalisation

Decision Feedback Equaliser (DFE): PCIe 4.0 and later versions

Testing Scope:

Accuracy of de-emphasis ratio

Improvement in eye diagram after equalisation

Equaliser convergence performance

5. Stress Eye Diagram Testing

Simulates the most severe operating conditions by injecting noise and interference at the receiver end to validate receiver tolerance.

Test Items:

Bit error rate (BER) testing with added noise

Receiver tolerance testing

Performance evaluation under varying channel losses

II. Test Equipment and Tools

Hardware Equipment

1. High-performance oscilloscope

Keysight DSOV334A (33GHz)

2. Bit error rate tester (BERT)

Keysight M8040A (64 Gbaud)

Software Tools

Eye diagram analysis software

S-parameter post-processing tools

Simulation software (e.g., ADS, HFSS)

Automated Test Scripts

III. Practical Test Case

Recently, we conducted PCIe signal integrity testing. The test scope included:

Capturing eye diagrams using a high-speed oscilloscope to verify signal eye height and width compliance with specifications.

Measuring total jitter (TJ) and random jitter (RJ) via a jitter analyser to validate sufficient jitter margin.

Evaluating metrics such as insertion loss and return loss using a vector network analyser to test S-parameters.

Following rigorous testing, all data conformed to PCIe protocol standards, demonstrating excellent link performance with satisfactory results.

IV. Conclusion

The introduction of new standards such as PCIe 6.0 and CXL (Compute Express Link) presents heightened challenges for signal integrity testing. PAM4 modulation, increased data rates, and more sophisticated equalisation techniques necessitate continuous advancement in testing methodologies and equipment.

Our company specialises in high-speed digital signal testing, offering comprehensive PCIe test solutions and extensive engineering expertise. Should you encounter any issues with PCIe signal integrity testing, we welcome your enquiries for discussion.

PCIe signal integrity testing is a critical step in ensuring the reliability of high-speed data transmission. Through systematic testing methodologies, specialised equipment, and rich experience, we can effectively identify and resolve signal integrity issues, thereby safeguarding product performance and reliability.